|
TVMC tuning for M55/U55 (MPS3-AN547) Arm FPGA Board
|
|
1
|
172
|
January 18, 2024
|
|
[TIR] Any Infra to support Block Rasterization?
|
|
0
|
127
|
January 17, 2024
|
|
TVMError: LLVM cpu architecture `-mcpu=rocketlake-avx512` is not valid in `-mtriple=x86_64-unknown-linux-gnu`
|
|
0
|
169
|
January 16, 2024
|
|
Tvm target cuda\rocm
|
|
0
|
142
|
January 5, 2024
|
|
Does TVM have a visual interface or a place where you can see the optimization process?
|
|
1
|
197
|
December 27, 2023
|
|
Libdarknet2.0.so is not compatible with arm64
|
|
2
|
445
|
December 26, 2023
|
|
Flattening a cache_read created buffer
|
|
6
|
268
|
December 11, 2023
|
|
[TIR] Register own TIR scheduling primitive
|
|
0
|
181
|
December 8, 2023
|
|
[TIR] tir schedule compute_at will break the block split steps, its different from te schedule, is that what we expect?
|
|
4
|
226
|
December 8, 2023
|
|
MISRA compliance
|
|
1
|
218
|
December 5, 2023
|
|
[TensorIR] Describing schedulable piece-wise reduce - Affine binding
|
|
3
|
192
|
December 1, 2023
|
|
The kernel or script crashed when loading ONNX by tvm
|
|
0
|
253
|
November 30, 2023
|
|
Memory Manager: Handling offset param in AllocNDArray
|
|
3
|
188
|
November 28, 2023
|
|
What is the point of annotations in TIR
|
|
0
|
228
|
November 23, 2023
|
|
MetaSchedule documentation?
|
|
4
|
499
|
November 17, 2023
|
|
How to get HardwareParams on the pltform
|
|
0
|
136
|
November 9, 2023
|
|
How to set the target when tuning for amd gpus
|
|
0
|
155
|
November 9, 2023
|
|
ExecuTorch in the context of TVM
|
|
1
|
387
|
November 7, 2023
|
|
How can set target with more detail information
|
|
0
|
150
|
November 7, 2023
|
|
"Output must be attached at root" with cache_write
|
|
4
|
216
|
November 6, 2023
|
|
Got error while compiling GPT-2 in tvm
|
|
2
|
344
|
October 31, 2023
|
|
[Maybe A Bug] Failed for using vectorize stage
|
|
1
|
524
|
October 27, 2023
|
|
On-the-fly weight validation with TVM
|
|
0
|
205
|
October 25, 2023
|
|
For learning , where to buy Arm(R) Cortex(R)-M55 CPU and Ethos(TM)-U55 NPU
|
|
4
|
922
|
October 25, 2023
|
|
The process of generating c code?
|
|
0
|
155
|
October 24, 2023
|
|
Combining/Fusing TensorIR blocks from different primfuncs
|
|
4
|
373
|
October 20, 2023
|
|
What should I do or How to use the c code after I generate it
|
|
0
|
141
|
October 20, 2023
|
|
How do I use the code I generate
|
|
9
|
533
|
October 19, 2023
|
|
[CODEGEN]About custom the c code
|
|
0
|
158
|
October 12, 2023
|
|
How to solve this problem?
|
|
0
|
178
|
October 11, 2023
|
