Block Diagram for Chisel VTA

Since Chisel based VTA has brought more details in the implementation, I think it might be necessary to have a overview of the design, so that it could be easier to dive into the the optimization and debugging.

Here is a draft of the block diagram of current implementation in Chisel VTA.

Here is another diagram describing “VTA Datapath” in the pipelined design. It’s generated from a Yosys JSON format file here, and can be improved interactively here.

Please bring your ideas in improving this, to make people easier to understand the design of VTA.

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Thanks @liangfu for starting this discussion. Are you mainly looking for an automatically generated block diagram of the design, or would you rather want to have a human-drawn block-diagram of the design that can be used as reference documentation?

I think firrtl-diagrammer should be an excellent choice to automatically generate detailed diagram of the design, but it isn’t straight forward to see stages in the pipeline and Bundles in the interconnections. Overwhelming wires in the diagram would make it less easier to understand. Therefore, I think what i’m looking for is a human-drawn block diagram that can be used as a reference documentation.

Here is an update to the diagram that I posted earlier.

Now, it’s much easier to see the inputs and outputs of Fetch, Load, Compute, and Store stages in the architecture.

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This is a pretty good block diagram - I wonder if we can have something in the middle. Here’s a hand drawn diagram that can be updated (which you have already seen before):

Do you want to represent all of the signals / buses accurately?

Can you elaborate a bit more?

Yes, I’m trying to describe all the signals / buses as precisely as possible, so that the block diagram could reflect the implementation in Chisel VTA.

Gotcha - what I mean was a hand-drawn figure that follows precise hardware schematics as autogenerated by the tools.