Since Chisel based VTA has brought more details in the implementation, I think it might be necessary to have a overview of the design, so that it could be easier to dive into the the optimization and debugging.
Here is a draft of the block diagram of current implementation in Chisel VTA.
Here is another diagram describing “VTA Datapath” in the pipelined design. It’s generated from a Yosys JSON format file here, and can be improved interactively here.
Please bring your ideas in improving this, to make people easier to understand the design of VTA.