Deploying a TVM model with LLC options

#1

I’ve been trying to follow these instructions, but for RISCV.

Specifically, this line:

if local_demo:
    target = 'llvm'
else:
    target = 'llvm -target=armv7l-linux-gnueabihf'

The instructions said these options correspond to llc and will recognize -mcpu, -mtriple, etc, so I tried this:

    # target = 'llvm -target=riscv64-unknown-linux -mtriple=riscv64 -mcpu=generic-rv64 -mattr=+64bit,a,c,d,f,m'

However I get this error:

'generic' is not a recognized processor for this target (ignoring processor)
'generic' is not a recognized processor for this target (ignoring processor)
'generic' is not a recognized processor for this target (ignoring processor)
'generic' is not a recognized processor for this target (ignoring processor)
'generic' is not a recognized processor for this target (ignoring processor)
'generic' is not a recognized processor for this target (ignoring processor)
[15:35:11] /home/asamara/tvm/src/codegen/llvm/codegen_llvm.cc:75: Set native vector bits to be 128 for riscv64
LLVM ERROR: Cannot select: 0x22c7228: ch = brcond 0x22a3438, 0x22c6e18, BasicBlock:ch<assert_end 0x22bc260>
  0x22c6e18: i64 = setcc 0x22c7430, Constant:i64<2>, seteq:ch
    0x22c7430: i64 = and 0x22c6fb8, Constant:i64<4294967295>
      0x22c6fb8: i64,ch = CopyFromReg 0x22a3438, Register:i64 %14
        0x22c6f50: i64 = Register %14
      0x22c73c8: i64 = Constant<4294967295>
    0x22c6db0: i64 = Constant<2>
In function: addone

And when I try the 32-bit version I get this:

'generic' is not a recognized processor for this target (ignoring processor)
'generic' is not a recognized processor for this target (ignoring processor)
'generic' is not a recognized processor for this target (ignoring processor)
'generic' is not a recognized processor for this target (ignoring processor)
'generic' is not a recognized processor for this target (ignoring processor)
'generic' is not a recognized processor for this target (ignoring processor)
[15:41:12] /home/asamara/tvm/src/codegen/llvm/codegen_llvm.cc:75: Set native vector bits to be 128 for riscv32
LLVM ERROR: Unable to lowerGlobalAddress

It looks like these errors are coming from a bug in LLVM, but I can’t be sure, is this even the correct way to deploy it?

#2

Ignore the above.
After updating to the latest version of TVM I actually get this error instead:

/home/username/tvm/src/codegen/llvm/codegen_llvm.cc:75: Set native vector bits to be 128 for riscv64
LLVM ERROR: Unable to lowerGlobalAddress
#3

Lowering (inside of the LLVM codegen) of a global address in LLVM for RISCV only works for non-PIC models. TVM explicitly sets the relocation model to PIC (see src/codegen/llvm/llvm_common.cc):

  llvm::TargetMachine* tm = target->createTargetMachine(
      target_triple, mcpu, mattr, opt, llvm::Reloc::PIC_);
2 Likes
#4

Is this specific to certain models? Is there a way to make sure that a model is not Position Independent?

#5

The word “model” in my reply referred to the “relocation model”, i.e. PIC or non-PIC. TVM requires PIC and the RISC-V backend in LLVM does not handle global addresses in PIC at the moment, so there is not much that you can do.