Functional, architecture, performance simulation for VTA


To ‘accelerate’ the development of hardware accelerators the VTA simulation environment needs to broaden. The current functional simulator is ok to show-case the state-change API and to demonstrate the functional transformations, but it isn’t enough to create an ABI or HAL. For that we would need an architecture simulator.

To facilitate design exploration of execution data flow and resource management, the environment would need a performance simulator that can model the execution pipeline of the VTA.

For embedded applications, a power simulator would be useful as well, to facilitate performance per Watt design explorations.

Right now (before releasing v1.0.0) the architecture simulator is the most important as TVM needs a clean hardware abstraction layer to decouple VTA engineering exploration. In particular, there are no primitives to communicate schedules between TVM and VTA.


Is the architecture simulation environment open?We want to explore other architectures based on vta.


There is an active effort (RFC to be released soon by @vegaluis) on providing cycle accurate simulation of the VTA hardware design. For now, we provide software emulation libraries that are open sourced, but don’t provide a cycle accurate accounting of what goes on within the chip. The benefit for these software emulation libraries is that they give us very fast emulation (infinite speed simulation as some would call it). This can give you metrics on how many times the tensor core was invoked, how much data was moved from DRAM to SRAM etc. But it won’t give us cycle accurate information of what goes on inside of the hardware pipeline.

With the new simulation effort, we’ll leverage Verilator to get both decent performance, as well as better visibility into the hardware behavior. Stay tuned for Luis’ upcoming RFC.


is it there yet, is it there yet…

Can’t wait to try that out.