Functional, architecture, performance simulation for VTA


To ‘accelerate’ the development of hardware accelerators the VTA simulation environment needs to broaden. The current functional simulator is ok to show-case the state-change API and to demonstrate the functional transformations, but it isn’t enough to create an ABI or HAL. For that we would need an architecture simulator.

To facilitate design exploration of execution data flow and resource management, the environment would need a performance simulator that can model the execution pipeline of the VTA.

For embedded applications, a power simulator would be useful as well, to facilitate performance per Watt design explorations.

Right now (before releasing v1.0.0) the architecture simulator is the most important as TVM needs a clean hardware abstraction layer to decouple VTA engineering exploration. In particular, there are no primitives to communicate schedules between TVM and VTA.