How to adjust VTA data type signed integer width to 16


Hello, I have a question about VTA hardware.
The configuration parameters for vta are as follows
“TARGET” : “pynq”,
“HW_VER” : “0.0.1”,
“LOG_BATCH” : 0,
“LOG_BLOCK” : 3,
The vta.bit was successfully compiled, and TVM was also successfully compiled, but the result of calculation was overflow. Is it because the “LOG_ACC_WIDTH” was set to be small? However, when I change “LOG_ACC_WIDTH” to 6, a compilation error will occur. Please help me solve this problem,thanks!


@zhuyong if you are using 16 bit weight/activations, a 32bit accumulator will most likely overflow. Indeed a solution would be to make the accumulator wider to 64 bit, but it seems like the test library complains about the fact that we are shifting a long long var by 64bits.

To get software infrastructure to work and support 64bit we’d need to change the implementation of the test library. Perhaps a workaround is to steer away from wide types (larger than 32 bits) for now.

Is the reason for using 16 bit weights because 8 bits affects accuracy too much? Would using HP16 instead be preferred since a those can be accumulated in a FP32 accumulator? This will require some work to get hardware/software support, but I believe would be preferable to the INT16/INT64 option.


Thank you for your reply,It is true that 8 bits affect the accuracy too much, so I still want to try it with 16 bits. How do I adjust the test library? Can you describe it in detail?


One option if you just want to launch complication is to skip simulation by setting the MODE=skip_sim when building the hardware. The bug we are getting with when using 64bit datatypes occurs in packing/unpacking:

One workaround is to actually add packing support for 64bit data types as a corner case since this code will only work on types that are 32, 16, 8, 4, 2, and 1 bit wide.