Question regarding the VTA implementation


#1

Hello,

I am a master student who is currently dealing with deep learning accelerator simulator design. I have implemented the physical model of computing units mainly some Matrix multiply array and got one cache simulator avaliable now. What i need to do now is to build the model for activiation function unit, pooling unit and algebra calculation unit for error back propogate plus the datapath to connect these components all toghther. I found the architecture and datapath is good in VTA while my research target is for new device based on emerging non-voltale technology. So i mainly plan to use the part without compute unit. My plan is to condigure the bandwidth of bus according to the size of DL model then generate the RTL code for latency/area/power information. Can i ask is this a plasiblue plan? Which files should i look into to change them to delete the compute unit while not influence the HLS process to generate RTL and also make it OK for further simulation process.

Many thanks!
Edward


#2

For design exploration of processor hardware there is typically a progression of models: functional simulator, architecture simulator, performance simulator, power simulator, and finally the RTL: fsim/asim/psim/rtl

For inference architectures, performance per Watt of full benchmarks is where we are going. So, your simulators need to be able to accurately execute benchmarks like ResNet, etc.:

Here is a reference to some of that DL benchmarking universe: https://github.com/DL-Benchmarks/DL-Benchmarks

Back to your question: the VTA definition is lacking any sequencing control capability, that is, the fsim is a hard-coded loop. To get to a proper fsim/asim/psim we need to define an architectural model of the accelerator and then start implementing asim and psim models. None of this is here right now, so there is going to be a lot of churn in this part of the system. My suggestion is to decouple yourself and your simulators from TVM for the moment, and focus on your own needs. Once the TVM/VTA interface stabilizes, you can write an adapter to your simulator.