In tvm/vta/tsim_example, I can get vcd file by modify “USE_TRACE=1” in chisel makefile. Next, I want to simulate VTA by tsim and hope to get vcd file. So, I modify vta/config/vta_config.json “TARGET” : “tsim”, and build tvm again. Then run vta/tutorials/matrix_multiply.py but there are somethings error. TVM is the lastest version. When I set “TARGET”: “sim”, it can work. emmm, did I do anything error?
It worked for me. The error indicates the VTA hardware is trying to access an address outside of virtual address space. I suggest using latest stable version of Verilator.
Hi liangfu! Thanks your suggestion! After checking, I found my environment have two verilator, one is installed by apt which is in /usr/share/verilator, other is installed by source which is in /usr/local/verilator. The reason maybe $(VERILATOR_INC_DIR) doesn’t set correctly. Now it worked for me too. Thank you!