[VTA] Define a complete Architecture Specification for VTA


VTA can be a software emulation, a hardware accelerator, or a remote high-performance distributed memory cluster. To decouple TVM from the different incarnations VTA implementations can take, we need to define a complete architecture specification for the VTA that can be used by a Hardware Abstraction Layer to define a working and portable interface between TVM and VTA implementations.

The architecture specification needs to contain:

1- a resource model
a: memory model
b: communication channels (concurrency levels)
c: command set (ISA)
d: notification channels (concurrency levels)
e: notification command set
f: bi-directional interrupt and panic and reset commands
g: debug protocol
h: diagnostics architecture and command set
i: internal state transfer

2- a boot protocol
a: initial state definition
b: power-up sequence

3- a programming model
a: execution control
b: concurrency (level and control)
c: bi-direction interrupt/synchronization control

4- a debug/diagnostic protocol
a: capability model (start/stop/reset, single step, break points, panics, conditionals, etc.)
b: state transfer