Question: I’m trying to generate a bitstream for Pynq-Z1 using the Chisel source code instead of using the HLS as given in the tutorial.
Things I have already done:
VTA.DefaultPynqConfig.v from Chisel source.
For now I’m gui of
Vivado 2018.3. I have created IP for the top level XilinxShell ensuring that the part number of Pynq is correct.
For reference, I have also created the bitstream using
vivado_hls. After opening this project, in the block design, I have noticed that the structure of Vta HLS is different from the chisel (eg: Vta HLS does not contain VCR or VME).
I’m facing issues trying to interface the chisel generated Vta hardware. Any solutions or tips with regards to this would be of great help.