Development


Functional, architecture, performance simulation for VTA (1)
tvm.ir_pass.IRTransform doesn't recurse when pre_order makes a change (3)
[RELAY] Injective ops do not work with tuple (8)
[Bug] CoreML frontend fails on NNVM with opt_level=3 and target=CUDA (1)
Compile failure after successfull auto-tune (2)
MXNet SSD Model Compiled to TVM SSD Model (6)
[Codegen][CUDA] Bug in global barrier (13)
[Hybrid] variables on CUDA should have 'local' scope (1)
[SOLVED][Relay] Global reduce fails to compile (4)
[Solved][Relay] Flaky compilation behavior (3)
Is there anything like "unlikely"? (2)
[Code Base] Understanding schedule.normalize() (1)
Flaky Test Cases Thread (2)
Cache_write does not replace vars in reducer identity (3)
Reason (and alternatives) for some min/max simplification rules (4)
[TVM Compiler] Performance measurement for TVM compiler pipeline (3)
[Graph IR] Comparison between Relay, NNVM and others (4)
The display is not fluent when I use TVM opencl on RK3288 (3)
Should Relay infers type by default in the ExprMutator? (2)
Should tvm share object among the Halide Call? (4)
Get multiple outputs efficiently (3)
[SOLVED] Android_rpc_test.py failed (10)
[TVM Compiler] "stack overflow" happens on Linux x64 when computation graph is "big" (3)
Compiling SSD for CUDA target seg faults (5)
tutorial SSD model inference error when set target to mali (3)
[RELAY] Buffer reuse in strided slice (2)
Tensorflow Frontend fill op error (4)
[Relay] Duplicated MaxPool in multiple branches (12)
Variable shape input support for code generation (10)
Tensorflow fill op convert issue (3)