I am trying to port the VTA-Chisel on CYCLONE V board and had a couple of issues when trying to create the bitstream.
http://www.terasic.com.tw/cgi-bin/page/archive.pl?CategoryNo=167&No=1081
The AXI (Lite and Full) implementation in the chisel/ seem to be Axi3 specification (they lack a AXPROT) and a couple of other signals.
Is there something we are missing?
Hi @ashriram,
Yes, you’re right. Intel only implemented AXI3 as the interface between SOC and FPGA on Cyclone V SoC.
Please check out the latest version of TVM from the master branch, there has been an update here, which compiles Chisel VTA directly for Cyclone V SoC. It takes AXI pins in AXI.scala for both AXI-Lite and AXI (AXI-Lite on Cyclone V SoC is actually still AXI3), and constrain the burst length in 4 pins instead of 8 pins in AXI4. Therefore, it implements AXI3 for Intel FPGA. In addition, the compilation script has been tested on DE10Nano, which is similar to your target board DE10Standard.
If you’re interested, there’s also an implement of VTA driver for Intel FPGA, which uses an in-house built contiguous memory allocation (CMA) implementation for DMA on FPGA. (See here for the driver and here for the CMA kernel module)
Good luck!