Hi, I am trying HLS-based Custom VTA Bitstream Compilation for Ultra96 PYNQ. But it seems that timing constraints are not met when bitstream compilation completed - vta_wrapper_timing_summary_routed.rpt tells it. (vta_wrapper_timing_summary_routed.rpt is in tvm/vta/build/hardware/xilinx/vivado/ultra96_1x16_i8w8a32_15_15_18_17/vta.runs/impl_1 directory)
- master branch of commit 77c4774857269768e775444dd1e0ac4c22801cb6 (Tue Jan 7 15:28:26 2020 -0800)
Vivado and Vivado HLS:
- Ubuntu 16.04.6 LTS
- overwrite vta_config.json with ultra96_sample.json in tvm/vta/config directory
- cd tvm/vta/hardware/xilinx and make
Is this a known issue or is there any operation mistake of mine?
I noticed that timing constraints are not met when operating frequency of vta is 333MHz (default configuration), but are met when down to 300MHz. To do this, I just modified value of fpga_freq from 333 to 300 in tvm/vta/python/vta/pkg_config.py and did make again.