Dear Developers,
I have modified the vta.cc
by trying to apply some additional #pragma such as:
#pragma HLS array_partition variable=out_mem cyclic factor=4 dim=1
in order to partition the array, and have created additional modules which are called within the load/compute/store function. Overall, the interface of the VTA module is still the same, but interfaces of load, compute, store module have slightly changed, taking a few more additional arguments:
void some_function(...) {
...
}
void compute (..., out_mem, additional arguments) {
#pragma HLS array_partition variable=out_mem cyclic factor=4 dim=1
...
some_function();
...
}
void store (..., out_mem) {
#pragma HLS array_partition variable=out_mem cyclic factor=4 dim=1
...
}
void vta(...) {
...
}
But during running the HLS and Vivado script (make in the xilinx
folder), it gave me the error:
~/tvm/vta/hardware/xilinx$ make
...
...
INFO: [xilinx.com:ip:fifo_generator:13.2-5968] /store_queueExecuting the post_config_ip from bd
INFO: [Device 21-403] Loading part xc7z020clg484-1
WARNING: [BD 5-232] No interface pins matched 'get_bd_intf_pins compute_0/out_mem_V_PORTA'
ERROR: [BD 5-106] Arguments to the connect_bd_intf_net command cannot be empty.
ERROR: [Common 17-39] 'connect_bd_intf_net' failed due to earlier errors.
while executing
"connect_bd_intf_net -intf_net compute_0_out_mem_V_PORTA [get_bd_intf_pins compute_0/out_mem_V_PORTA] [get_bd_intf_pins $out_mem/BRAM_PORTA]"
invoked from within
"if {${out_part} > 1} {
for {set i 0} {$i < ${out_part}} {incr i} {
# Create instance: out_mem, and set properties
set out_mem [ create..."
(procedure "create_root_design" line 141)
invoked from within
"create_root_design "" $clock_id $inp_part $wgt_part $out_part $inp_bus_width \
$inp_mem_depth $wgt_bus_width $wgt_mem_depth $out_bus_width $out_mem_..."
(file "~/tvm/vta/hardware/xilinx/scripts/vivado.tcl" line 929)
Vivado% q
INFO: [Common 17-206] Exiting Vivado at Wed May 29 21:19:23 2019...
Question: Could you kindly point me out what the problem is and where I should look into? To my best understanding, the interface of compute
module seems to change, possibly due to the #pragma array_partition
, and thus the original vivado.tcl
script cannot find it. If I understood correctly, where should I find this port name and how should I fix it?